1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having a synchronous dynamic random access memory (hereinafter referred to as an SDRAM), which is a DRAM operating in synchronization with a clock and, in particular, to a double data rate (hereinafter referred to as DDR) SDRAM.
2. Description of the Related Art
An SDRAM carries out an internal memory operation in synchronization with an external clock. A regular SDRAM receives and transmits one piece of data per clock cycle. In contrast, in a DDR SDRAM, a clock is divided so as to receive and transmit one piece of data at both the rising edge and falling edge of the clock. Accordingly, the DDR SDRAM has double the data rate compared to the regular SDRAM. The DDR SDRAM includes a DDR-I SDRAM and a DDR-II SDRAM, which is an advanced version of the DDR-I SDRAM.
In the DDR-I SDRAM, a write latency WL is a constant value of “1” (i.e., WL=1). The write latency WL refers to the number of clock cycles tCK required from a time when a write command and an aDDRess are input to a semiconductor integrated circuit device (chip) to a time when data to be written at the aDDRess is input to the semiconductor integrated circuit device (chip).
The DDR-II SDRAM, new standard, is allowed to include an additive latency AL, which is a variable value, as the write latency WL. This allows the write latency WL to vary up to its maximum value of 8. Also, this significantly increases the time period for holding an externally input aDDRess signal in the semiconductor integrated circuit device (chip), and therefore, this increases the number of required circuits. The increase in the number of circuits must be suppressed.
FIG. 1 shows waveforms of a write operation in a DDR-I SDRAM, which is a semiconductor integrated circuit device of a first related art.
As shown in FIG. 2, the DDR-I SDRAM, which is a semiconductor integrated circuit device of the first related art, includes an input buffer 11 and a command decoder 12 connected to the input buffer 11. The input buffer 11 inputs a clock input CLK, a command, and an aDDRess and then outputs an aDDRess PA (refer to “PA” in FIG. 1) and a clock PACLK (refer to “PACLK” in FIG. 1). The command decoder 12 decodes a write command (WRITE in FIG. 1) received via the input buffer 11 and then outputs the decoded output MDCAT. A column aDDRess latch circuit 13 inputs the clock PACLK, the aDDRess PA, and a latency control signal LCS, latches the aDDRess PA, and outputs a column aDDRess CAT (refer to “CAT” in FIG. 1). A YS (Y Selection: column selection) latch circuit 14 inputs the decoded output MDCAT and the latency control signal LCS, latches the decoded output MDCAT, and outputs a YS (column selection) control signal MDCAYST (refer to “MDCAYST” in FIG. 1).
As described above, in FIG. 1, a DDR-I SDRAM has a write latency of constant value “1”. Assuming that one clock cycle is represented by tCK, the DDR-I SDRAM has a waiting time including a clock cycle for inputting a write command WRITE into the chip and the subsequent one clock cycle (i.e., WL+tCK=2 tCK). In the subsequent one clock cycle, the DDR-I SDRAM writes data to a memory cell at an aDDRess input to the chip at the same time as input of the write command (WRITE). That is, in one clock cycle after 2 tCK (=WL+tCK) has elapsed, the data is written to the memory cell specified by the aDDRess. As a result, the aDDRess must be held for a period of 3 tCK including the clock cycle for writing the data to the memory cell specified by the aDDRess.
As shown in FIG. 2, to fulfill this requirement, the DDR-I SDRAM must include a 3-bit latency counter circuit 20 having six series-connected latch circuits (F/F #0, . . . , F/F #5 in FIG. 1) per aDDRess.
The reason is as follows: In a DDR-I SDRAM, data is written to a memory cell after two clock cycles (constant value) have elapsed since the input of a write command into the chip. Therefore, the aDDRess for writing the data must be held in the chip until three clock cycles have elapsed since the input of the write command. In this case, if an aDDRess holding circuit is composed of D (delay) flip-flops (F/Fs) as described below, six D flip-flops are required as shown by F/F #0, . . . , F/F #5 in FIG. 1. Two D flip-flops connected in series can hold an aDDRess for one clock cycle when the clock PACLK and an inverted phase of the clock PACLK are input. Here, a set of two D flip-flops (F/F) represents 1 bit and six D flip-flops (F/F) represent 3 bits.
As shown in FIG. 2, a 2-bit output selector 21 is connected to the output of the 3-bit latency counter circuit 20. The output selector 21 is controlled by the latency control signal LCS, a read control signal MCRDT, and a write control signal MCWRT so as to output the output of the latency counter circuit 20 as a column aDDRess CAT in response to different predetermined latencies in accordance with a read operation and a write operation.
The YS (column selection) latch circuit 14 includes a 3-bit latency counter circuit 30, which receives the decoded output MDCAT, and a 2-bit output selector 31. The 3-bit latency counter circuit 30 has the same configuration as the 3-bit latency counter circuit 20, while the 2-bit output selector 31 has the same configuration as the 2-bit output selector 21.
The output of the 3-bit latency counter circuit 30 is connected to the 2-bit output selector 31. The output selector 31 is controlled by the latency control signal LCS, the read control signal MCRDT, and the write control signal MCWRT so as to output the output of the latency counter circuit 30 as a YS control signal MDCAYST in response to different predetermined latencies in accordance with a read operation and a write operation.
FIG. 3 shows waveforms of a write operation in a DDR-II SDRAM, which is a semiconductor integrated circuit device of a second related art.
As shown in FIG. 4, the DDR-II SDRAM, which is a semiconductor integrated circuit device of the second related art, includes an input buffer 110 and a command decoder 120 connected to the input buffer 110. The input buffer 110 inputs a clock input CLK, a command, and an aDDRess and outputs an aDDRess PA (refer to “PA” in FIG. 3) and a clock PACLK (refer to “PACLK” in FIG. 3). The command decoder 120 decodes a write command (“WRITE” in FIG. 3) received via the input buffer 110 and then outputs a decoded output MDCAT. A column aDDRess latch circuit 130 inputs the clock PACLK, the aDDRess PA, and a latency control signal LCS, latches the aDDRess PA, and outputs a column aDDRess CAT (refer to “CAT” in FIG. 3). A YS (column selection) latch circuit 140 inputs the decoded output MDCAT and the latency control signal LCS, latches the decoded output MDCAT, and outputs a YS (column selection) control signal MDCAYST (refer to “MDCAYST” in FIG. 3).
FIG. 3 shows operational waveforms indicating the waveforms from the input signals to the chip (DDR-II SDRAM) to the YS (column selection) initiation signal. The DDR-II SDRAM adopts a new method known as Posted/CAS (Column ADDRess Strobe) and an additive latency AL is added as a parameter of the method. The suffix “/CAS” represents a column aDDRess strobe. The Posted/CAS method allows a column command such as READ and WRITE to be input to the chip in advance. After a predetermined latency set for AL has elapsed, the READ or WRITE command is issued inside the chip. In addition, the write latency WL has a variable value determined by AL and a /CAS latency CL. Here, the write latency WL can be expressed as WL=(AL+CL−1). When AL=4 and CL=5, the current maximum value of the write latency WL is 8 (i.e., WL=AL+CL−1=4+5−1).
In the DDR-II SDRAM, data is written to a memory cell at a specified aDDRess after (WL+2 tCK) clock cycles have elapsed since the input of a write command into the chip. For example, when the write latency WL is 8 (i.e., WL=8), the operation is as follows. The DDR-II SDRAM has a waiting time including 8 (=WL) clock cycles from a first clock cycle for inputting a write command WRITE into the chip to an eighth clock cycle and 2 clock cycles (2 tCK) subsequent to the eighth clock cycle. In the subsequent one clock cycle, the DDR-II SDRAM writes data to a memory cell at the aDDRess input to the chip at the same time as input of the write command WRITE. That is, in one clock cycle after 10 tCK (=WL+2 tCK) has elapsed, the data is written to the memory cell specified by the aDDRess. As a result, the aDDRess must be held for a period of 11 tCK including the clock cycle for writing the data to the memory cell specified by the aDDRess.
As shown in FIG. 4, to fulfill this requirement, the DDR-II SDRAM must include an 11-bit latency counter circuit 200 having 22 series-connected latch circuits (F/F #0, . . . , F/F #21 in FIG. 3) per aDDRess, thus significantly increasing the number of circuits.
The reason is as follows: The DDR-II SDRAM requires a maximum of 11 clock cycles, which is a current specification, from the input of a write command into the chip to the data writing to a memory cell. Therefore, the aDDRess must be held in the chip for 11 clock cycles.
If an aDDRess holding circuit is composed of the above-described D (delay) flip-flops (F/Fs), 22 D flip-flops are required, as shown by F/F #0, . . . , F/F #21 in FIG. 3. In addition, since the number of D flip-flops must be variable, additional circuits are required to change the number of D flip-flops.
As shown in FIG. 4, the outputs of the 11-bit latency counter circuit 200 are connected to an 11-bit output selector 210. The output selector 210 is controlled by a latency control signal LCS to output the output of the latency counter circuit 200 as a column aDDRess CAT.
The YS (column selection) latch circuit 140 includes an 11-bit latency counter circuit 300, which receives the decoded output MDCAT, and an 11-bit output selector 310. The 11-bit latency counter circuit 300 has the same configuration as the 11-bit latency counter circuit 200, while the 11-bit output selector 310 has the same configuration as the 11-bit output selector 210.
The outputs of the 11-bit latency counter circuit 300 are connected to the 11-bit output selector 310. The output selector 310 is controlled by the latency control signal LCS so as to output the output of the latency counter circuit 300 as a YS control signal MDCAYST.
Additionally, Japanese Unexamined Patent Application Publication No. 2000-276877 discloses an SDRAM having a posted CAS latency function as an SDRAM related to the two above-described related arts. Furthermore, Japanese Unexamined Patent Application Publication No. 2002-25255 discloses a double data rate SDRAM and Japanese Unexamined Patent Application Publication No. 2002-133866 discloses an SDRAM having a posted CAS function.